The present invention relates to a method of fabricating a semiconductor device by which a thickness of an oxide film is prevented from being relatively thinned at the boundary between a shallow trench isolation and a thick gate oxide film when a process of fabricating a dual gate oxide is applied to a normal shallow trench isolation.
Since power devices such as a liquid crystal display (LCD) driver IC (LDI) require both low voltage (LV) operation for driving an associated logic circuit, together with high voltage (HV) operation for driving the LCD during operation, associated gate oxide films are formed of a dual gate type. Also, the continuous trend toward ever-miniaturized line width requires the use of a shallow trench isolation (STI) process.
However, if the process for fabricating the dual gate oxide film is conducted in the same manner as it is applied to the STI structure, excessive numbers of STI recesses in the LV region are created during formation of the dual gate oxide film for the HV region, resulting in compromise of the overall device characteristics.
The source of the recesses lies in that since a CVD oxide film such as USG or HDP is used as a gap fill in the STI structure, and since a thermal oxide film is used as a gate oxide film, a severe dent is created in the boundary between the active region and the field region due to the difference in wet etch rate between the thermal oxide film and CVD oxide film.
This conventional process is explained in greater detail with reference to FIGS. 1a through 1c, which illustrate the process of fabricating the conventional dual gate oxide film.
For convenience"" sake, the process is explained by being classified into 3 steps as follows.
In the drawings, reference symbol xe2x80x9cIxe2x80x9d indicates a first active region in which a thin gate oxide film for LV is formed and reference xe2x80x9cIIxe2x80x9d indicates a second active region in which a thick gate oxide film for HV is formed.
First Step
As shown in FIG. 1a, a nitride film pattern (not shown) is formed in the first and second active regions I, II of the substrate 10. The silicone substrate 10 is selectively etched to a predetermined thickness by using the pattern as mask so that trench (t) is formed in the field region within the substrate 10. The CVD oxide film of USG or HDP material is formed on the resultant material so that the trench (t) is sufficiently filled. Next, the CVD oxide film is chemically mechanically polished so that the nitride pattern in the first and second active regions I, II may remain and thereafter the nitride film is removed. The STI 12 that buries the inside of the trench (t) is thus formed. Subsequently, CMOS well ion-implantation and channel ion-implantation are performed. The first thermal oxide film 14 for HV is subsequently formed to a thickness of 300 xc3x85 in the active regions I, II on the substrate 10.
Second Step
As shown in FIG. 1b, a photo-resist pattern 16 is formed on the resultant structure so that the first active region I and the surrounding STI 12 are partially exposed. The first thermal oxide film 14 is wet etched using the pattern as a mask and selectively remains only in the HV region II.
Third Step
As shown in FIG. 1c, the photo-resist pattern 16 is removed and the second thermal oxide film 18 for LV is formed to a thickness of 40 xc3x85 in the first active region I. Thereby, the process for the dual gate oxide film is completed. In this process, when the second thermal oxide film 18 is formed, the first thermal oxide film 14 also grows to a small degree. However, since the amount of the growth is minor, the resultant effect is negligible.
As a result, the first active region I is formed therein with a relatively thin gate oxide film of the second thermal oxide film 18 material, which is suitable for the LV region. The second active region II is formed therein with a relatively thick gate oxide film of the first thermal oxide film 14 material, which is suitable for an HV region.
However, if the dual gate oxide film is formed through the aforementioned processes, a number of limitations result during the formation of device.
When the first thermal oxide film 14 of LV region I is removed by using the photo-resist pattern 16 as a mask, the STI 12, which is indicated by xc3xa2 in FIG. 1b, surrounding the perimeter of the LV region is recessed together with the first thermal oxide film 14. Accordingly, a dent is generated in the region, that is, in the region of the boundary surface between the active region and the field region. FIG. 2 shows the structure of a device having such defect.
Such a defect phenomenon is caused by the difference in a wet etch rate between the first thermal oxide film 14 being used as a gate oxide film and the CVD oxide film forming the STI 12. For example, in the case where the STI 12 is filled with a HDP material, the depth of recess is approximately 200 xc3x85 relative to the substrate 10 of the active region. In contrast, in the case where the STI 12 is filled with a USG material, the recess amounts to approximately 1,000 xc3x85 relative to the substrate 10 of the active region, thereby the dent is more severely created.
In the case where the dent is formed, poly residue remains in the region that is recessed during etching of the gate poly as a follow up process, or the gate poly surrounds the field region and the active region at the boundary between the field region and the active region. Each of these scenarios results in deterioration in the gate oxide film due to the concentration of electric field created in upward and sideward directions as well as deterioration in characteristics such as drop in threshold voltage Vth of a resulting transistor during the operation of device, increase in threshold voltage leakage, and decrease in punching margin.
In order to solve those problems, there has been disclosed a process technique by which a dual gate oxide film is formed using a nitride film without the need for removing the thick thermal oxide film of the LV region while the process of fabricating the dual gate oxide film is applied to a normal STI structure in LDI design.
FIGS. 3a through 3e sequentially illustrate a sequence of forming a dual gate oxide structure. The method comprises five steps as follows.
Reference symbol xe2x80x9cIxe2x80x9d indicates a LV region in which a relatively thin gate oxide film is formed, and reference symbol xe2x80x9cIIxe2x80x9d indicates a HV region in which a relatively thick gate oxide film is formed.
First Step
As shown in FIG. 3a, the STI 102 of the CVD oxide film material that buries the inside of the trench (t) is formed in the field region on the silicone substrate 100 by the same method as shown in FIG. 1a. The buffer oxide film 104 of the thermal oxide film material is subsequently formed in the active regions I, II on the substrate 100 and CMOS well ion-implantation and channel ion-implantation are performed. While the buffer oxide film 104 remains, the nitride film 106 is formed on the buffer oxide film 104 including the STI 102. Thereafter, the CVD oxide film 108 of medium temperature oxide (MTO) is formed on the resultant material. Here, the MTO refers to an oxide film that is formed at the temperature of 700 to 800xc2x0 C. The buffer oxide film 104 is formed at a thickness of 100 to 120 xc3x85, the nitride film 106 is formed at a thickness of 90 to 110 xc3x85 and the CVD oxide film 108 is formed at a thickness of 90 to 110 xc3x85.
Second Step
As shown in FIG. 3b, the CVD oxide film 108 is patterned by a photo-resist pattern 110 so that the first active region I and the surrounding STI 102 are partially masked. The second active region II and the adjacent CVD oxide film 108 are wet etched with the pattern 110 as a mask.
During the third step shown in FIG. 3c, the photo-resist pattern 110 is removed.
During the fourth step shown in FIG. 3d, the nitride film 106 and the buffer oxide film 104 are in order etched by utilizing, as a mask, the residual CVD oxide film 108, thereby exposing the surface of the second active region II. At this time, the nitride film 104 is etched by a wet etching method in which phosphoric acid is used as etchant.
The residual CVD oxide film 108 that used as a mask is simultaneously removed when the buffer oxide film 104 is etched. The first thermal oxide film 112 is formed at a thickness of 400 to 450 xc3x85 on the exposed surface of the second active region II.
During the fifth step shown in FIG. 3e, the nitride film 106 and the buffer oxide film 104 that remain in the first active region I and the adjacent STI 102 are in order etched, thereby exposing the surface of the first active region I.
In this case, since a portion of the first oxide film 112 is also consumed during the etching process (particularly, etching of the buffer oxide film), the first thermal oxide film 112 only remains in a thickness of approximately 250 to 350 xc3x85 on the second active region II when the etching processes on the residual films are completed. The second thermal oxide film 114 is formed in a thickness of 30 to 50xc3x85, thinner than the first thermal film 112 on the exposed surface of the first active region I. Thereby, the processes for the dual gate oxide film are completed. Again, in this example, when the second thermal oxide film 114 is formed, the first thermal oxide film 112 of the second active region II also grows to a small degree. However, since the amount of the growth is minor, the resultant effect is negligible.
As a result, the first active region I is formed therein with a thin gate oxide film for LV of the second thermal film 114 material, and the second active region II is formed therein with a thick gate oxide film for HV of the first thermal film 112 material.
In the case that the dual gate oxide film is fabricated according to such a method, dents can be prevented from being created at the boundary between the active region and field region because the process of removing the thick thermal oxide film in the LV region is not needed during the formation of the thick gate oxide film in the HV region.
However, when the thick gate oxide film of the first thermal oxide film 112 grows in the second active region II by using the nitride film 106 as a mask during this process, there is a problem in that the first thermal oxide film 112 grows to a relatively thinner degree in the boundary region (indicated by {circle around (b)} in FIG. 3e) between the STI 102 and the active region, than in other adjacent portions. That is, the first thermal oxide film 112 is critically thin at the edge portion of the STI 102. The thicker the gate oxide film, the more pronounced the phenomenon. FIG. 4 shows the structure of the device including such a defect. In the drawing, the symbol xe2x80x9clxe2x80x9d indicates the predetermined thickness of the first thermal oxide film 112, and xe2x80x9cl-xcex1xe2x80x9d indicates the thickness of the first oxide film 112 at the boundary as a result of the thinning phenomenon.
The thinning phenomenon arises due to the fact that compressive stress is concentrated on the side of the STI 102 that is relatively stiff during the thermal oxidation process. When such a thinning phenomenon occurs, the resulting gate oxide film is deteriorated due to the concentration of electric field. In addition, a transistor is commonly formed at the center of the active region with channels (the channel of flat TR) and turned-on just after a transistor is first formed at the boundary of the active region and field region with channels (the channel of corner TR) and turned-on. This phenomenon, referred to as the xe2x80x9chumpxe2x80x9d phenomenon, causes the resulting transistor to appear as though it has two threshold voltage Vth values, which should be avoided.
Accordingly, it is an object of the present invention to provide a semiconductor device fabricating method by which the LOCOS profile characteristic is applied to an edge portion of a STI in an HV region to thereby lower compressive stress that is concentrated on the side of the STI. As a result, the present invention prevents a thinning phenomenon of a gate oxide film at edge portions of the STI that would otherwise occur when the gate oxide film for HV grows in a normal STI structure by utilizing a nitride film as a mask. This prevents compromise of the operational characteristics, which otherwise would be caused by the concentration of electric field, combined with the hump phenomenon.
In order to achieve the above object, the present invention is directed to a semiconductor device fabricating method. A semiconductor substrate is formed having a first active region and a second active region that are isolated by a shallow trench isolation (STI) structure. A buffer oxide film is formed in the first and second active regions on the substrate and a nitride film is formed on the buffer oxide film and the STI. A first photo-resist pattern s formed on the nitride film to expose a portion of the STI and edges of the adjacent second active region. Unmasked portions of the buffer oxide film and the nitride film are etched to open the edges of the second active region to a predetermined size, and thereafter the first photo-resist pattern is removed. A field oxide film is formed in contact with the STI on the opened portion of the second active region by performing an oxidation process using residual nitride film as a mask. A CMOS well ion-implantation and a channel ion-implantation are the performed and a CVD oxide film is formed on the resultant structure. A second photo-resist pattern is formed on the CVD oxide film to mask a portion the STI and the adjacent first active region, and the CVD oxide film that is not masked by the second photo-resist pattern is etched to thereafter remove the second photo-resist pattern. The nitride film and buffer oxide film are then etched by utilizing the residual CVD oxide film as a mask so that the nitride film and buffer oxide film remain in the first active region and are opened in the second active region. A first thermal oxide film for a gate oxide film is formed on the second active region, and the nitride film and the oxide film that remain in the first active region are then etched to thereby open the first active region. A second thermal oxide film for a gate oxide film is formed at a thickness less than the thickness of the first thermal oxide film on the opened portion of the first active region.
In a preferred embodiment, the STI is formed with a CVD oxide film of USG or HDP. The nitride film is preferably formed at a thickness ranging from 50 to 3,000 xc3x85. The field film is preferably formed at a thickness ranging from 100 to 4,000 xc3x85. The first thermal oxide film is preferably formed at a thickness ranging from 80 to 1,000 xc3x85. The second thermal oxide film is preferably formed at a thickness ranging from 30 to 50 xc3x85. The buffer oxide film is preferably formed of a thermal oxide film material. The CVD oxide film is preferably formed of a MTO (Medium Temperature Oxide) material. The MTO (Medium Temperature Oxide) is preferably formed at the temperature ranging from 700 to 800xc2x0 C.
The first active region may comprise a LV region, and the second active region may comprise a HV region. The HV region may be designed to operate at an internal voltage of 3.3 to 50 V.
According to the aforementioned method, since the processes of fabricating the gate oxide film for HV are performed such that a field oxide film is additionally formed on the edge portion of STI for HV, compressive stress that is concentrated on the sides of the relatively stiff STI during the oxide process can be lowered relative to the conventional technique, thereby preventing the gate oxide film for HV from being thinned at edge portions of the STI.